This invention is in the field of logic latches or flip-flops and more specifically to high speed R-S (reset, set) latches.
The operation of R-S latches is well understood in the art. The output of the latch remains in a predetermined logic state until an appropriate set or reset pulse appears at the corresponding input. In "Introduction to Switching Theory and Logical Design" (2nd Ed., John Wiley & Sons, 1974), the authors, Fredrick J. Hill and Gerald R. Peterson have described the operation of an R-S latch. "A pulse on the S [set] input will `Set` the flip-flop--that is, drive the Q output to the 1 level and the Q output to the 0 level. A pulse on the C [reset] line will `Clear` (Reset) the flip-flop--that is, drive the Q output to the 0 level and the Q output to the 1 level." p. 214
One typical prior art R-S latch design is shown in FIG. 1. The schematic has been simplified for ease of analysis. The prior art R-S latch includes an input stage consisting of FETs 14 and 16 which are biased by current source 18. The drains of the input FETs are coupled to load impedances 10 and 12, which are shown as resistors. A differential voltage is developed across the drains of FETs 14 and 16. The R-S latch further contains a latch stage consisting of FETs 20 and 22, and an output stage consisting of FETs 24 and 26, which are biased by current sources 19 and 21.
Assuming that the prior art R-S latch is in the set mode, the Q output will be high or at a logic 1 state, and the Q output will be low or at a logic 0 state. A reset pulse is now required to switch the states of the outputs. A reset pulse will cause FET 14 to conduct which will cause the voltage at the drain of FET 14 to decrease. The output stage, which includes FET 24, which is biased in a source follower configuration, will simply track this decreasing voltage. Thus, the Q output of the R-S latch will closely track the reset pulse.
The analysis of the Q output is quite different. The Q output cannot change state until the Q output has substantially reached a logic 0 state, in which case the latch stage will switch. Only after the latch stage has switched, will the voltage at the gate of FET 26, and consequently the Q output, reach a logic 1 level. Put another way, as FET 14 begins to conduct, it alone causes the Q output to start changing logic state. After the delay from the R input to the Q output has propagated, then FETs 20 and 22 assist in the switching action, thus speeding up the transition. If the resistive loads 10 and 12 had been active loads with appropriate clamping circuitry, then the Q output would not begin changing logic state until the clamping circuit had ceased clamping due to the reduced current flowing through FET 20. At that time, however, the Q output would be well into the downward transition to a logic 0 level.
The response of the prior art R-S latch to a reset pulse is shown in FIG. 2. It may be easily seen that the Q output switches first, whereas a finite delay exists until the Q output switches.
In high speed logic circuits, delays between the Q output and Q output are undesirable for the very fact that extra delay in such circuits necessarily decreases maximum frequency of operation. Also, the delay may cause undesirable race conditions and unnecessarily complicates system design.
Therefore, what is desired is an R-S latch that does not have a delay between the Q and Q outputs, but switches logic states symmetrically, and at high speeds.